1. Field of the Invention
The present invention relates to a circuit carrier, and more particularly to a circuit carrier adapted for a pin grid array (PGA) package.
2. Description of the Related Art
Due to advance of technology, a variety of electronic products have been developed. These electronic products with multiple functions are more portable and available for users, and have small sizes. Circuit carriers have been widely used in circuit layout for these electronic products. The circuit carrier can be, for example, printed circuit boards (PCB) or IC substrates. The circuit carrier is composed of a plurality of patterned circuit layers and a plurality of dielectric layers that are alternatively stacked with each other. Each dielectric layer is disposed between two patterned circuit layers. These patterned circuit layers are connected to each other with plated through holes (PTH) or micro vias. Due to having high layout density, convenient package process and high electrical performance, the circuit carrier has been popularly applied to various electrical packages like ball grid array (BGA) package or PGA package.
FIG. 1 is a cross sectional view showing a conventional Flip Chip (FC)/PGA package. The package adopts a surface mounting technology (SMT) pinning technology. The FC/PGA package comprises a circuit carrier 100 and a chip 180. The circuit carrier 100 comprises a substrate 110, at least one pin pad 120, a solder mask layer 140, at least one pin 150 and at least one solder layer 160. The pin pad 120 is disposed over the surface 112 of the substrate 110. The solder layer 140 is disposed over the surface 112 of the substrate 110, having at least one solder mask opening 140a for exposing the pin pad 120. One end of the pin 150 connects to the pin pad 120 through the solder layer 160. The chip 180 connects to the surface 114 of the substrate 110 via the bumps 170. An underfill 190 is filled between the chip 180 and the substrate 110.
SMT has been used to connect two devices. The solder layer usually comprises Sn/Pb alloy because of its good soldering properties. By the concern of environmental pollution caused by Pb, some countries will forbid the use of Sn/Pb alloy and replace it by lead free solder in the near future. The reflow temperature for the lead free solder is higher than that for lead containing solder, such as Sn/Pb alloy. The change will impact reliabilities of electronic devices bonded with SMT.
Referring to FIG. 1, the bumps 170 comprise lead free solder and the pin 150 is fixed to the pin pad 120 with the solder layer 160, which is a lead free solder, too. In order to melt the bumps 170 or the pre-solders thereunder, the reflow temperature is about 260° C. When the reflow temperature is higher than the melting point of the solder layer 160, the solder layer 160 melts and the pin 150 cannot be fixed to the pin pad 120 due to the melting of the solder layer 160. Without the help of the solder layer 160, the shift or disposition of the pin 150 occurs. As a result, the yield of manufacturing the electrical package declines.